1. Field of The Invention
The present invention relates generally to an apparatus for polishing a substrate to be flattened. Specifically, the present invention relates to an apparatus for polishing a substrate for semiconductive integrated circuits having many notches generated on the surface thereof to obtain an evenly flattened surface.
2. Description of the Background Art
Recently, multilaying a substrate for a circuit of a semiconductor, for example, a silicon semiconductor, is progressed according to microrizing and ultra high integrating of semiconductive integrated circuits. In order to multilay the circuit substrates, the surfaces of the substrates must be completely flattened. Commonly, certain kinds of flattening techniques have been known, as shown in Table 1. However, each technique has several disadvantages for flattening of the circuit substrates, which will be described as follows, though they have a measure of advantage for use.
Glass coating, using spin on glass (SOG) or such, can be easily accomplished. Throughput of glass materials is excellently smooth. However, when the circuit is microrized, cavities are generated in a groove formed thereon. On the other hand, when the circuit is thickened, cracking of the coating occurs. On the other hand, organic film coating results good surface planarity of the substrate with little cracking. However, a certain difficulty arises in processing of coating caused by moisture absorbability and toxicity of the coating material and large amount of polarization derived therefrom. Lamination of an inorganic film combined with an organic film also results good surface planarity of the substrate. However, moisture absorbability and toxicity of the coating materials also cannot be disregarded. Further, processing steps are increased compared with coating only with the organic film.
TABLE 1 ______________________________________ Flattening Techniques for Interlayer Insulation Film ______________________________________ Coating Glass (SOG) Coating Organic Film (PIQ) Coating Inorganic/Organic (PIQ) Laminating Reflowing Doped Oxide Reflowing Etching Etchback Contact Hole Tapered Etching PVD Bias Sputtering CVD Plasma CVD ECR CVD ______________________________________
Reflowing technique is no problem in processing, however, high temperatures are required for processing and microrizing of the circuit is very difficult.
Etchback technique has excellent processibility, electrical and chemical stabilities. However, processing is very complicated and, when the circuit is microrized, cavities are generated in a groove formed thereon. Tapered etching of contact holes can also be stably accomplished. However, form controllability is insufficient. Further to say, processing steps are multiplied.
Bias sputtering results in good planarity of the circuit surface. However, the base element of the circuit tends to be damaged and multiproductivity is insufficient.
Plasma chemical vapor deposition (CVD) and ECR CVD are effective for flattening of the circuit surface because coating materials can sufficiently deposit on microrized grooves formed on the circuit. Further, ECR CVD can be accomplished at ordinary temperatures to obtain good coating with little damage. However, both CVD techniques have insufficiencies in their multiproductivity and relative specular planarity.
CVD as shown in Table 1 has been frequently utilized with etchback technique similarly shown in Table 1. An insulation film is formed by CVD technique, then the surface thereof is planary etched to obtain the plane surface. The process of CVD combined with etchback is now described in detail. A CVD film formed of SiO.sub.2, or such appropriate materials, is thickly laminated on a wiring, for example, an aluminum wiring, as an interlayer insulator. A coating film for flattening, which is selected from coating materials such as a resist and a spin on glass (SOG), is applied on the CVD film and the surface of the coating film is flattened. Then, blanket etchback of the coating film and the CVD film is accomplished under the condition of 1:1 of the etch rate. However, processing for flattening is complicated to obtain the completely plane surface. Additionally, area ratio of cross section of the coating film and the insulation (CVD) film is altered according to the progressing of etchback, because the insulation film is laminated according to the configuration of the wiring, while the upper surface of the coating film is flattened. Therefore, etching rate is slightly fluctuated by the microloading effect. Regulation of etch rate of both films to 1:1 is thus difficult.
In order to simplify the flattening processing while maintaining etching rate constantly, a polishing technique has been applied to flatten the substrate surface. Polishing is the technique which has been conventionally utilized in the art of specular finishing of wafers (Si substrates), and recently, in the art of silicon on insulator (SOI) devices.
"Trench Isolation by Selective Epi and CVD Oxide Cap" J. Electrochem. SOC., Vol.137 No.12, Dec., 1990 discloses a study of flattening of an insulation film including the steps of laminating a CVD film on an aluminum wiring as an interlayer insulator to be substantially thickened, and polishing the CVD film by a polishing machine to obtain a plane surface of the film. A wafer (substrate) is put on a polishing plate having a polishing pad thereon and is rotatably supported by a shaft. Polishing agent (hereinafter, described as slurry) is supplied to the circumference of the wafer via a slurry supply port concurrently with polishing the surface of the wafer. During polishing, the wafer is pressurized toward the polishing pad by a polishing pressure control device via a wafer retainer which is rotatably supported by a wafer supporting shaft. Slurry is supplied by a slurry supply system. When polishing the wafer by the aforementioned polishing machine, the wafer surface is polished from the circumference toward the center thereof because slurry is supplied from the circumference of the wafer. Therefore, slurry supplied from the slurry supply system cannot sufficiently reach the center portion of the wafer. Thus, the polishing of the wafer circumference is progressed greater than that of the center thereof. The difference of polishing degree between the circumference and the center portion of the wafer surface increases with decreasing pressure applied to the wafer toward the polishing pad.
In order to overcome the aforementioned disadvantages, Japanese Utility Model First Publication (not allowed) No.63-754 discloses a polishing machine having a plurality of holes as slurry supply ports to uniformly supply slurry from a slurry supply system to a wafer surface. The slurry supply ports are concentrically made on a wafer polishing pad through a polishing plate. The polishing speed of the wafer surface can be control to be even at any position of the wafer surface with uniformly supply of slurry via the slurry supply ports. Japanese Patent First Publication (not allowed) No.2-100321 by the same applicant of the present invention discloses a polishing machine including a plurality of slurry supply ports as disclosed in the aforementioned Japanese Utility Model First Publication, and a wafer polishing pad formed of a porous material having successive holes therein. Slurry can be uniformly supplied from a slurry supply system to the wafer surface via the slurry supply ports and the porous polishing pad. Thus, the polishing speed of the wafer surface can be controlled to be even at any position of the wafer surface with a uniform supply of slurry. According to the aforementioned improved polishing machines, slurry is directly supplied to the wafer surface. Therefore, the wafer surface becomes plane, while that it becomes relatively convexed when slurry is supplied from the circumference of the wafer surface.
However, several problems have arose with increasing wafer diameter. Pressure applied to the wafer toward the polishing pad placed on the polishing plate becomes greater at the center portion of the wafer surface than that at the circumference thereof. When slurry is directly and uniformly supplied to the wafer surface, uniformity of polishing may not be obtained, or even, the wafer surface may be concaved.